1. Technical Field
The present invention relates to microprocessors and, in particular, to mechanisms for controlling power consumption in microprocessors.
2. Background Art
Modern processors include extensive execution resources to support concurrent processing of multiple instructions. A processor typically includes one or more integer, floating point, branch, and memory execution units to implement integer, floating point, branch, and load/store instructions, respectively. Register files and on-chip caches are also provided to supply the execution resources with operands. When fully engaged by an executing program, these resources can create significant power dissipation problems.
Instruction code sequences that include enough instructions of the correct type to fully engage a processor's execution resources for significant intervals are relatively rare. Smart compilers and out of order execution can only extract so much instruction level parallelism (ILP) from most code. To conserve power, a processor may employ a clock gating mechanism to cut off the clock signal delivered to execution resources or their components that are not used by an executing code sequence. Such a processor can engage extensive resources as needed, e.g., to support code sequences with high ILP, without dissipating large amounts of power when code sequences with more typical ILP levels execute.
For code sequences having high ILP, few if any resources can be gated off, and the processor can dissipate significantly greater power than it does running code characterized by more typical ILP. To accommodate power-hungry code, a processor may be run at less than its top performance level by, for example, limiting its operating frequency. Hobbling the processor in this manner leaves a thermal margin for those code sequences that cause the processor to dissipate large amounts of power.
An alternative strategy, called power throttling, allows the processor to operate at its top performance level by default and reduces (throttles) the performance level if the processor's power consumption becomes too great. Power throttling may be implemented through a number of mechanisms. These include altering the number of instructions processed per clock cycle (instruction throughput) or altering the voltage and/or the frequency at which the processor operates (operating point). These and other power control mechanisms have their particular advantages and disadvantages.
Power dissipation scales quadratically with processor voltage, making adjustment to voltage levels a potent tool for controlling processor power. Power dissipation scales linearly with the processor's clock frequency. However, frequency and voltage are typically adjusted together, because the maximum frequency is limited by the voltage drive available at transistor gates. Further, the latency for operating point adjustments is significantly greater than the time scale on which a processor's power consumption can change, making it a relatively course mechanism for managing these changes. Power dissipation scales linearly with instruction throughput. Adjustments to instruction throughput may be implemented with lower latency than operating point changes, but they may not be sufficient to offset a change in power consumption.
The present invention addresses these and other problems associated with monitoring and controlling power consumption by processor and other programmable devices.